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description the a8513 is a single-output white led (wled) driver for lcd backlighting. it integrates a current-mode boost converter with an internal power switch and one current sink. the a8513 can operate from a single power supply from 4.5 to 40 v, to accommodate start/stop, cold crank, and load dump requirements. a 2 mhz boost converter switching frequency allows the a8513 to operate above the am radio band. if required, the fault flag can be used as part of a circuit to drive an external p-fet to disconnect the input supply from the system in the event of a fault. the a8513 provides protection against output short and overvoltage, open or shorted diode, open or shorted led pin, shorted boost switch or inductor, shorted i set resistor, and ic overtemperature. a dual level cycle-by- cycle current limit function provides soft start and protects the internal current switch against high current overloads. the a8513 is provided in a 10-pin msop package (suffix ly) and a 16-pin tssop package (suffix lp). both packages have an exposed thermal pad for enhanced thermal dissipation, and are lead (pb) free, with 100% matte tin leadframe plating. a8513-ds rev. 2 features and benefits ? aec-q100 qualified ? wide input voltage range of 4.5 to 40 v for start/stop, cold crank and load dump requirements ? boost converter switching frequency up to 2 mhz, allowing operation above the am band ? excellent input voltage transient response ? internal secondary ovp for redundant protection ? fully integrated led current sink and boost converter with 60 v dmos fet ? maximum led current of 150 ma ? drives up to 14 series leds ? single en/pwm pin interface for pwm dimming and enable function ? 5000:1 pwm dimming at 200 hz wide input voltage range, high efficiency fault tolerant led driver packages: typical application circuit not to scale a8513 continued on the next page? 10-pin msop with exposed thermal pad (ly package) 16-pin tssop with exposed thermal pad (lp package) applications: ? lcd backlighting for: ? automotive infotainment ? automotive cluster ? automotive center stack ? industrial lcd displays ? portable dvd players ? flatbed scanners ? led lighting sw ovp vout r ovp1 r ovp2 vin vdd c vdd c out en/pwm iset gnd comp led fault pad a8513 v c r iset c in l1 d1 c p v in r z (optional) c z (optional) boost f sw (mhz) v in (min) (v) leds per string (max) 0.25/0.5/1 5 14 21014 2812 26 9 25 7
wide input voltage range, high efficiency fault tolerant led driver a8513 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit led pin v led ?0.3 to 55 v ovp pin v ovp ?0.3 to 60 v vin and f a u l t pins v in , v fault -0.3 to 40 v sw pin v sw continuous ?0.6 to 60 v t < 50 ns ?1.0 v iset pin v iset ?0.3 to 5.5 v all other pins ?0.3 to 7 v operating ambient temperature t a range k ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the elec trical characteristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reli ability. features and benefits (continued) selection guide part number oscillator frequency, f sw (mhz) packing* package a8513klytr-t 2 4000 pieces per 13-in. reel 10-pin msop with exposed thermal pad A8513KLYTR-1-T 1 contact factory for availability a8513klytr-2-t 0.5 a8513klytr-3-t 0.25 a8513klptr-t 2 4000 pieces per 13-in. reel 16-pin tssop with exposed thermal pad a8513klptr-1-t 1 contact factory for availability a8513klptr-2-t 0.5 a8513klptr-3-t 0.25 *contact allegro ? for additional packing options ? fault flag pin to alert the controller to a myriad of possible fault conditions ? protection features: ? shorted output ? open or shorted led pin ? output undervoltage and overvoltage ? input undervoltage ? shorted boost switch or inductor ? shorted i set resistor ? open boost schottky ? overtemperature
wide input voltage range, high efficiency fault tolerant led driver a8513 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com lp package ly package pin-out diagram terminal list table name number function lp ly comp 15 10 output of the error amplifier and compensation node. connect compensation network from this pin to gnd for control loop compensation. f a u l t 64 this pin is used to indicate fault conditions. logic low indicates that the a8513 has a fault present. gnd 13,14 9 ground. iset 12 8 connect the r iset resistor between this pin and gnd to set the 100% led current level. led 10 6 connect the cathode of the led string to this pin. nc 1,2,8,9,16 ? no connection. ovp 4 2 this pin is used to sense an overvoltage condition. connect a resistive divider from the vout node to this pin to adjust the overvoltage protection (ovp). pad ? ? exposed pad of the package providing enhanced thermal dissipation. this pad must be connected to the ground plane(s) of the pcb with at least 8 thermal vias, directly in the pad. en/pwm 11 7 pwm dimming pin. used to control led intensity by using pulse width modulation. sw 3 1 the drain of the internal nmos switch of the boost converter. vdd 7 5 output of internal ldo. connect a 0.1 f decoupling capacitor between this pin and gnd. vin 5 3 input power to the a8513. sw ovp vin fault vdd comp gnd iset en/pwm led 1 2 3 4 5 10 9 8 7 6 pad nc nc sw ovp vin fault vdd nc nc comp gnd gnd iset en/pwm led nc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pad thermal characteristics* may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance (junction to ambient) r ja lp package on 4-layer pcb based on jedec standard 34 oc/w on 2-layer pcb with 3.8 in. 2 of copper area each side 43 oc/w ly package on 4-layer pcb based on jedec standard 48 oc/w on 2-layer pcb with 2.5 in. 2 of copper area each side 48 oc/w package thermal resistance (junction to pad) r jp 2 oc/w *to be verified by characterization. additional thermal information available on the allegro ? website.
wide input voltage range, high efficiency fault tolerant led driver a8513 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vdd regulator uvlo internal soft start enable pwm enable short led detect iset fault led driver 1.235 v ref driver circuit internal v cc internal v cc v ref internal v cc v ref v ref i ss thermal shutdown i ss 100 k enable current sense diode open sense ovp sense oscillator sw vin comp en/pwm gnd iset ovp led fault + ? + ? + ? + ? functional block diagram
wide input voltage range, high efficiency fault tolerant led driver a8513 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 valid at v in = 16 v, t a = 25oc, indicates specifications guaranteed through the full operating temperature range with t a = t j = ?40oc to125 oc, typical specifications are at t a = 25oc; unless otherwise specified characteristics symbol test conditions min. typ. max. unit input voltage specifications operating input voltage range v in 4.5 ? 40 v vin pin uvlo start threshold v uvlorise v in rising ?? 4.35 v vin pin uvlo stop threshold v uvlofall v in falling ?? 3.90 v vin pin uvlo hysteresis v uvlohys ? 450 ? mv input current input quiescent current i q en/pwm = v ih , sw = 2 mhz, no load ? 5 ? ma input sleep supply current i qsleep vin = 16 v, en/pwm = 0 v ? 110 a input logic levels (en/pwm and f a u l t 3 ) input logic level (low) v il 5 v < v in < 40 v ?? 400 mv input logic level (high) v ih 5 v < v in < 40 v 1.5 ?? v en/pwm pull-down resistor r en/pwm en/pwm = 5 v ? 100 ? k f a u l t pin pull-down voltage v fault i fault = 0.5 ma ?? 0.4 v f a u l t pin leakage current i faultlkg v fault = 5 v ?? 1 a error amplifier open loop voltage gain a vol ? 45 ? db transconductance g m i comp = 10 a ? 990 ? a/v source current i ea(src) v comp = 1.5 v ? ?360 ? a sink current i ea(sink) v comp = 1.5 v ? 360 ? a comp pin pull-down resistance r comp f a u l t asserted ? 2000 ? output overvoltage protection overvoltage protection threshold v ovphi(th) measured at ovp pin 1.168 1.218 1.268 v ovp pin leakage current i ovph standard cmos input, measured at v ovp = 1.2 v ?? 100 na ovp pin undervoltage threshold v uvp(th) measured at ovp pin ?? 110 mv secondary overvoltage protection v ovp(sec) measured at sw pin 53 55.5 58 v boost switch switch on-resistance r ds(on)sw i sw = 750 ma, v in = 16 v ? 450 800 m switch leakage current i swlkg v sw = 16 v, en/pwm = v il , t a = t j between ?40oc and 85oc ? 0.1 1 ua v sw = 16 v, en/pwm = v il , t a = t j = 125oc ? 10 ? ua switch current limit i sw(lim) 1.9 2.2 2.8 a secondary switch current limit i sw(lim2) higher than i sw(lim) (max) in all conditions, a8513 latches when detected 3 3.5 4.64 a minimum switch on-time t sw(on) ? 75 100 ns minimum switch off-time t sw(off) ? 55 85 ns continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver a8513 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com oscillator frequency oscillator frequency f sw A8513KLYTR-1-T, a8513klptr-1-t 1.8 2 2.2 mhz a8513klytr-2-t, a8513klptr-2-t 0.9 1 1.1 mhz a8513klytr-3-t, a8513klptr-3-t 450 500 550 khz a8513klytr-4-t, a8513klptr-4-t 225 250 275 khz led current sinks led accuracy err led iset = 150 a ?? 3% led regulation voltage v led iset = 150 a ? 880 ? mv i set to i led current gain a iset iset = 150 a 1014 1045 1076 a/a iset pin voltage v iset ? 1.003 ? v allowable iset current i set 40 ? 160 a soft start led current gain a iledss current through enabled led pin during soft start ? 48 ? a/a maximum pwm dimming off-time t pwml measured while en/pwm = low during dimming control, and internal references are powered-on (exceeding t pwml results in shutdown) ? 16 ? ms minimum pwm on-time t pwmh first cycle when powering-up a8513 ? 1.5 3 s en/pwm high to led-on delay t dpwm(on) time between pwm enable and when led current reaches 90% of maximum; v pwm = 0 2 v ? 250 500 ns en/pwm low to led-off delay t dpwm(off) time between pwm enable going low and when led current reaches 10% of maximum; v pwm = 2 0 v ? 250 500 ns thermal protection (tsd) thermal shutdown threshold 2 t tsd temperature rising ? 165 ? oc thermal shutdown hysteresis 2 t tsdhys ? 20 ? oc 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), and posit ive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 3 f a u l t pin is high voltage tolerant electrical characteristics 1 (continued) valid at v in = 16 v, t a = 25oc, indicates specifications guaranteed through the full operating temperature range with t a = t j = ?40oc to125 oc, typical specifications are at t a = 25oc; unless otherwise specified characteristics symbol test conditions min. typ. max. unit
wide input voltage range, high efficiency fault tolerant led driver a8513 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance -55 -5 45 145 95 -55 -5 45 145 95 -55 -5 45 145 95 -55 -5 45 145 95 4.345 4.295 4.245 4.195 4.145 4.095 4.045 3.995 3.945 3.855 3.805 3.755 3.705 3.655 3.605 3.555 3.505 v uvlorise (v) v uvlofall (v) vin uvlo rising threshold voltage 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 switch frequency 10 9 8 7 6 5 4 3 2 1 0 i qsleep ( a) f sw (mhz) temperature (c) temperature (c) temperature (c) temperature (c) vin input sleep mode current versus ambient temperature versus ambient temperature versus ambient temperature vin uvlo falling threshold voltage versus ambient temperature v in = 40 v 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 e ? ciency, (%) input voltage, v in (v) e ? ciency versus input voltage i led = 90 ma, led v f 3.2 v e ? ciency versus input voltage i led = 150 ma, led v f 3.2 v 78 56 9 1112 14 10 13 15 16 17 18 19 21 20 22 input voltage, v in (v) 78 56 9 1112 14 10 13 15 16 17 18 19 21 20 22 e ? ciency, (%) 5 series leds; v out = 17 v 6 series leds; v out = 20 v 7 series leds; v out = 23 v 5 series leds; v out = 17 v 6 series leds; v out = 20 v 7 series leds; v out = 23 v
wide input voltage range, high efficiency fault tolerant led driver a8513 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com -55 -5 45 145 95 temperature (c) temperature (c) -55 -5 45 145 95 pwm dimming only pwm + ana l og dimming 100 10 1 0.1 0.10 151.0 150.8 150.6 150.4 150.2 150.0 149.8 149.6 led current ra o (%) pwm duty cycle (%) normalized led current ra o versus pwm duty cycle f pwm = 200 hz, v in = 12 v, 6 series leds ( 21 v, 150 ma) led current versus ambient temperature i led = 150 a 0.01 0.10 1 10 100 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 sw ch current, i sw (a) switch current limit versus ambient temperature led current, i led (ma)
wide input voltage range, high efficiency fault tolerant led driver a8513 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the a8513 incorporates a current-mode boost controller with internal dmos switch, and a single led current sink. it can be used to drive an led string of up to 14 white leds in series, with current up to 150 ma. for optimal efficiency, the output of the boost stage is adaptively adjusted to the minimum voltage required to power the led string. this is expressed by the fol- lowing equation: v out = v led + v reg (1) where v led is the voltage drop across the led string, and v reg is the regulation voltage of the led current sink (typically 0.88 v at the maximum led current). enabling the ic the ic turns on when a logic high signal is applied to the en/pwm pin (figure 1), and turns off when this pin is pulled to a logic low. for the device to be enabled, the voltage on the vin pin must be greater than v uvlorise to clear the undervoltage lock- out (uvlo) threshold (figure 2). before startup, the a8513 goes through a system check to determine if there are any fault condi- tions that would prevent the system from functioning correctly. powering up: led pin short to gnd check after the vin pin goes above v uvlorise , the ic checks if the led pin is shorted to gnd by pre-charging the led pin (figure 3). when the voltage on the led pin exceeds 260 mv, the a8513 proceeds with soft start. if a short is present on the led pin, the ic will not power up until the short is removed. at this time the output is also checked for a v out short, using the ovp pin. if the ovp pin does not rise above v ovplo(th) the ic will not power up. soft start function during soft start, the comp pin delivers a steady 80 ua current, the led pin current gain is set to a iledss . the lower gain will help limit the inrush current generated by charging the output functional description figure 1. start-up by slowly ramping up en/pwm with v in at 16 v; shows v out (ch1, 10 v/div.), i led (ch2, 50 ma/div.), comp (ch3, 1 v/div.), and en/pwm (ch4, 2 v/div.), time = 2 ms/div. figure 2. start-up by slowly ramping up v in with en/pwm at 2 v; shows v out (ch1, 10 v/div.), i led (ch2, 50 ma/div.), comp (ch3, 1 v/div.), and en/pwm (ch4, 2 v/div.), time = 2 ms/div. t v out en/pwm i led comp c4 c3 c1 c2 t v out en/pwm i led comp c4 c3 c1 c2 uvlo threshold exceeded figure 3. led detection period; shows f a u l t (ch1, 5 v/div.), v led (ch2, 1 v/div.), i led (ch3, 100 ma/div.), and en/pwm (ch4, 5 v/div.), time = 500 s/div. t en/pwm i led v led c4 c1 c2 c3 led detection fault
wide input voltage range, high efficiency fault tolerant led driver a8513 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com capacitors. after the a8513 senses there is enough voltage on the led pin, it increases the led current to the preset regulation current. the comp pin will continue to source 80 ua until the leds are able to run at the full preset current level. boost converter frequency the switching frequency of the boost regulator is preset internally to one of four frequencies. the frequency options are: part number switching frequency (f sw ) (mhz) A8513KLYTR-1-T 2 a8513klytr-2-t 1 a8513klytr-3-t 0.5 a8513klytr-4-t 0.25 led current setting and led dimming the led current, i led , is set using the iset pin, and can range from 40 to 150 ma. connect a resistor, r iset , between this pin and gnd to set the i led current, according to the following formula : i led = r iset a iset v iset = r iset 1045 1.003 v (2) where i led is in a and r iset is in . this formula sets the maximum current through the leds, which is referred to as the 100% current . pwm dimming the led current can be reduced from the 100% current level by pwm dimming using the en/pwm pin. when the en/pwm pin is pulled high, the a8513 turns on and the led pin sinks 100% current (figure 4). when en/pwm is pulled low, the boost con- verter and led sink are turned off. the compensation (comp) pin is floated, and critical internal circuits are kept active. the a8513 has very fast turn-on and turn-off times during pwm dimming to minimize low pwm duty cycle errors. the typical pwm signal delay t dpwm(on) is 250 ns (figure 5). the typical t dpwm(off) time, between the pwm signal and the led current going low, is shown in figure 6. analog dimming the a8513 can also be dimmed by using an external dac or other voltage source applied either directly to the ground side of the r iset resistor or through an external resistive divider to the figure 4. typical pwm dimming sequence, with pwm dimming frequency of 1000 hz and 10% duty cycle; shows comp (ch1, 1 v/div.), v led (ch2, 10 v/div.), i led (ch3, 100 ma/div.), and en/pwm (ch4, 5 v/div.), time = 500 s/div. figure 5. typical en/pwm signal (5 v/div.) to led current (100 ma/div.) turn-on delay. the delay measured about 250 ns. v in is 12 v, v out for 10 series leds is approximately 36 v, i led is 150 ma. (time = 500 ns/div.) figure 5. typical en/pwm signal (5 v/div.) to led current (100 ma/div.) turn-off delay. the typical delay is about 250 ns. (time = 500 ns/div.) t v led en/pwm i led comp c4 c1 c2 c3 t en/pwm i led c4 c3 t en/pwm i led c4 c3
wide input voltage range, high efficiency fault tolerant led driver a8513 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com iset pin. the limitation of this form of dimming is that the inter- nal i set error amplifier is designed to work from 40 to 160 a, thus limiting the dimming ratios that can be achieved. figure 7, top panel is a typical application using a dac to control the led current using a single resistor connected to the iset pin. the i set current is controlled by the following formula: i set = v iset ? v dac r iset (3) where v iset is the iset pin voltage and v dac is the dac out- put voltage. when the dac voltage is equal to v iset , the internal reference, there is no current through r iset . when the dac voltage starts to decrease, the iset current starts to increase, thus increasing the led current. when the dac voltage is 0 v, the led current will be at its maximum. ? for a dual-resistor configuration (lower panel of figure 7), the iset current is controlled by the following formula: i set = ? v iset r iset v dac ? v iset r 1 (4) the advantage of this circuit is that the dac voltage can be higher or lower, thus adjusting the led current to a higher or lower value of the preset led current set by the r iset resistor: ? v dac = 1.003 v; the output is strictly controlled by r iset ? v dac > 1.003 v; the led current is reduced ? v dac < 1.003 v; the led current is increased output overvoltage protection (ovp) and output undervoltage protection (uvp) the a8513 has output overvoltage protection (ovp), output undervoltage protection and secondary overvoltage protection (open diode). overvoltage protection the ovp pin has a threshold, v ovphi(th) , of 1.218 v. a resistive divider can be used to set the v out over- voltage protection threshold up to 45 v (see figure 8). there is no restriction on the value of the resistor chosen, but it is recom- mended that the divider current be kept between 10 and 60 a. this will minimize the effect of sense current on the accuracy of ovp, and minimize output voltage bleed-off during pwm dim- ming. formulas for calculating the ovp resistor voltage divider are shown below. r ovp1 = (v ovp ? 1.218 v) / i set (5) r ovp2 = 1.218 v / i set (6) the ovp function is not inherently a latched fault. if the ovp condition occurs during a load dump, the ic will stop switching but not shut down. figure 7. simplified diagram of voltage led current control (upper) single resistor, and (lower) dual resistors. figure 8. simplified diagram of the ovp pin functions. gnd dac vdac gnd a8513 iset gnd dac vdac gnd a8513 iset r iset r1 r iset ovp vout r ovp1 r ovp2 a8513 1.218 v 100 mv + ? + ?
wide input voltage range, high efficiency fault tolerant led driver a8513 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a b t v out en/pwm i led c4 c2 c1 c3 fault the ovp condition can become a latched fault if, during an ovp event, the led current is not in regulation. this typically occurs during an open led string situation. if both faults occur simul- taneously the ic will shut down and the fault flag will be set (see figures 9, 10, and 11). undervoltage protection the ovp pin is also used to detect output undervoltage protection (uvp) against v out short to gnd. when the uvp fault is tripped, the fault flag is set (fig- ure 12). using an external pmosfet interfaced to the f a u l t pin (figure 13), the user can disconnect the ic from vin during a fault event. figure 9. open led condition during pwm dimming. (a) the led string (ch3, 100 ma/div.) is opened (no current flow through the led pin) during an off-period for the pwm dimming signal (ch4, 5 v/div.). (b) at the next pwm cycle, the led open condition is detected and the a8513 starts boosting the output voltage (ch1, 10 v/div.). (c) upon reaching the ovp threshold and sensing no led current flow, the a8513 shuts down and sets the fault flag (ch2, 5 v/div.). (time = 10 ms/div.) figure 10. open led condition when pwm duty cycle is 100%. (a) the led string (ch3, 200 ma/div.) is opened (no current flow through the led pin). (b) the a8513 starts boosting the output voltage (ch1, 20 v/div.). (c) upon reaching the ovp threshold there is still no current flow through the led pin, and the a8513 shuts down and sets the fault flag (ch2, 5 v/div.). the led pin voltage is ch4, 2 v/div. (time = 50 s/div.) figure 11. power-up into an open led situation. (a) a8513 enabled, (b) fault flag (ch2, 5 v/div.) is set when ovp threshold is reached. shows v out (ch1, 20 v/div.), i led (ch3, 100 ma/div.), and en/pwm (ch4, 5 v/div.), time = 1 ms/div.. figure 12. input disconnect switch function during an output short. (a) v out (ch1, 10 v/div.) falls during vout short to ground, (b) high peak current present due to short, before the pmosfet (ch3, 5 v/div.) is disconnected. shows input current (ch2, 10 a/div.) and fault flag (ch4, 5 v/div.), time = 50 s/div. figure 13. typical circuit for input disconnect switch. t v out pmosfet gate i in c3 c4 c1 c2 fault a b 1 v in a8513 ao4421 2n7002 fault 5v l1 10 1k k k t v out en/pwm i led c4 c2 c1 c3 a b c fault a b c t v out i led v led c4 c1 c2 c3 a b c fault
wide input voltage range, high efficiency fault tolerant led driver a8513 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com secondary overvoltage protection the a8513 has secondary overvoltage protection for the internal boost switch in the event of an open diode condition. if the voltage on the sw pin exceeds the device safe operating voltage rating, the a8513 is disabled and remains latched off (figure 14). the en/pwm pin must be brought low longer than t pwml to clear this fault. boost switch overcurrent protection the boost switch is protected with cycle-by-cycle current limit- ing set to i sw(lim) (figure 15). there is also a secondary current limit that is sensed on the boost switch. when this current limit is exceeded, the a8513 immediately shuts down (figure 16). the secondary current limit is above the cycle-by-cycle current limit and protects the switch from destructive currents if the boost inductor is shorted. figure 14. secondary overvoltage protection tripped when the switching diode is opened during operation. (a) high voltage is detected on sw node (ch1, 20 v/div.) and the a8513 is shut down. (b) fault flag is set (ch2, 5 v/div.). shows led current (ch3, 100 ma/div.), time = 500 ns/div. t i led v sw c1 c2 c3 fault a b figure 15. cycle-by-cycle current limit, inductor current is c3 (1 a/div.). (a) fault flag (ch1, 5 v/div.) is not set during cycle-by-cycle current limit, (b) comp pin signal (c2, 2 v/div.) is close to 3.6 v. (time = 1 ms/div.) figure 16. secondary current limit during an inductor short condition. (a) limit is reached, (b) the ic shuts down and the fault flag is set. shows fault flag (c1, 5 v/div.), switch node voltage (c2, 20 v/div.), and current through the inductor (c3, 2 a/div.); time = 1 s/div. t i l v sw c2 c1 c3 fault a b normal operation inductor short a b c t comp i l c2 c1 c3 fault a b cycle-by-cycle inductor current limit
wide input voltage range, high efficiency fault tolerant led driver a8513 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com input uvlo when v in rises above the uvlo threshold v uvlorise , the a8513 can be enabled by asserting en/pwm. the a8513 is disabled when v in falls below v uvlofall ? v uvlohys for more than 1 s (figure 17). this 1 s lag prevents false shut downs during momentary glitches on the input power supply. vdd the vdd pin provides regulated bias supply for internal circuits. connect a capacitor, c vdd , with a value of 0.01 to 0.1 f to this pin. shutdown if the en/pwm pin is pulled low for more than t pwml , the device enters shutdown mode and clears all internal fault regis- ters. in shutdown, the a8513 will disable all current sources and wait until en/pwm goes high to re-enable the ic. figure 17. input uvlo. (a) uvlo tripped (v in , ch1, 2 v/div.), (b) fault flag set (ch2, 2 v/ div.). shows led current (ch3, 100 ma/div.) and en/pwm (ch4, 1 v/div.), time = 5 ms/div. a b t i led en/pwm v in c4 c1 c2 c3 fault a b
wide input voltage range, high efficiency fault tolerant led driver a8513 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fault protection during operation the a8513 constantly monitors the state of the system to deter- mine if any fault conditions occur. the response to a triggered fault condition is summarized in the table below. note: some of the protection features might not be active during startup, to prevent false triggering of fault conditions. the latching faults can be cleared in two ways: ? keep the en/pwm pin low for more than 16 ms. ? cycle the power to create a uvlo condition. fault behavior diagrams are shown in figures 18, 19 and 20. fault mode table fault name type active fault flag set description boost sink driver primary switch current protection (cycle-by-cycle current limit) auto-restart always no this fault condition is triggered by the cycle-by-cycle current limit i sw(lim) . prevents current in inductor from exceeding i sw(lim) . off for a single cycle on secondary switch current limit latched always yes when the current through the boost switch exceeds the secondary current sw limit, i sw(lim2) , the a8513 immediately shuts down. off off secondary ovp latched always yes secondary overvoltage protection is used for open diode detection. when diode d1 opens, the switch pin voltage will increase until v ovp(sec) is reached. off off led pin short protection auto-restart startup yes this fault prevents the a8513 from starting-up if the led pin is shorted to ground. after the short is removed, soft-start is allowed to begin. off off iset short protection auto-restart always yes this fault occurs when the i set current goes above 150% of the maximum allowable iset current, i set (max). the boost will stop switching and the ic will disable the led sinks until the fault is removed. when the fault is removed, the ic tries to regulate to the preset led current. off off led string open protection latched always yes this fault occurs when the ovp pin exceeds the v ovphi(th) threshold. the a8513 immediately stops switching. if at the same time, the led voltage is below regulation, the ic will shut down. off off output overvoltage protection auto-restart always no this fault occurs when the ovp pin exceeds v ovphi(th) threshold (for example, during a load dump). the a8513 immediately stops switching, but continues to sink current through the led pin. off on output undervoltage protection auto-restart always yes this fault occurs when the ovp pin senses less than 110 mv on the pin. off off overtemperature protection auto-restart always yes this fault occurs when the die temperature exceeds t tsd . off off vin uvlo na always yes until internal regulator shuts down this fault occurs when v in drops below v uvlofall . this fault resets all latched faults. off off
wide input voltage range, high efficiency fault tolerant led driver a8513 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com iset short to ground recovery from iset short to ground ovp tripped during load dump figure 18. f a u l t (ch1, 5 v/div.), v sw (ch2, 20 v/div.), i led (ch3, 100 ma/div.), and iset (ch4, 1 v/div.), time = 1 s/div. figure 20. v in (ch1, 20 v/div.), v out (ch2, 20 v/div.), and v sw (ch3, 20 v/div.), f a u l t (ch4, 5 v/div.), time = 2 ms/div. figure 19. f a u l t (ch1, 5 v/div.), i led (ch2, 100 ma/div.), and iset (ch3, 1 v/div.), time = 2 ms/div. a b t i led iset v sw c4 c2 c1 c3 fault a b t v out v in v sw c1 c3 c4 c2 fault t i led iset c3 c1 c2 fault
wide input voltage range, high efficiency fault tolerant led driver a8513 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example this section provides a method for selecting component values when designing an application using the a8513. a typical circuit using this design is shown in figure 21. assumptions: for the purposes of this example, the following are given as the application requirements: ? v in : 5 to 16 v ? quantity of series leds, # seriesleds : 6 ? led current, i led : 120 ma ? v f at 120 ma: 3.2 v ? f sw : 2 mhz ? t a (max): 85c ? pwm dimming frequency: 200 hz with a minimum duty cycle of 1%. procedure: select the appropriate configuration and the individual component values in an ordered sequence. step 1: connect the series led string from vout to the led pin. step 2: determine the value for the i led setting resistor, r iset : r iset = v iset a iset / i led (7) = (1.003 1045) / 120 ma = 8.74 k choose an 8.66 k resistor. step 3: determine the values of the ovp resistors. the ovp resistors are connected between the ovp pin and the output volt- age (vout) and the ovp pin and ground. step 3a: the first step is to determine the maximum voltage based on the led v f requirements. to this value the regulation voltage should be added, as well as another 2 v to account for noise, output ripple, and resistor tolerances. the regulation volt- age, v led , of the a8513 is 880 mv. then: v out(ovp) = # seriesleds v f + v led + 2 v (8) = 6 3.2 v+ 0.880 v + 2 v = 22.08 v to find the ovp resistor values, the user should choose a resis- tor divider that has very low current (i ovp ) and r ovp should be approximately 1 m . a good starting point is 50 a as i ovp . (the i ovp current is used later in calculating the total leakage current.) then : r ovp1 = ( v out(ovp) ? v ovphi(th) ) / i ovp (9) = (22.08 v ? 1.218 v) / 50 a = 417.2 k and: r ovp2 = v ovphi(th) / i ovp (10) = 1.218 v / 50 a = 24.36 k choose a value of resistor that is higher value than the calculated r ovp . in this case 422 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = r ovp i ovp v ovphi(th) (11) = 422 k 50 a + 1.218 v = 22.32 v step 3b: at this point a quick check should be done to determine if the conversion ratio is acceptable for the selected frequency: d maxofboost = 1 ? t sw(off) f sw (12) = 1 ? 85 ns 2 mhz = 83% where the minimum switch off-time, t sw(off) , is found in the electrical characteristics table. the theoretical maximum v out is then calculated as: v out (max) v d =? 1 ? d maxofboost v in (min) 0.4 v 29.01 v == ? 1 ? 0.83 5 v (13) where v d is the diode forward voltage. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, a lower frequency ver- sion of the a8513 should be chosen to meet the maximum duty cycle requirements. step 4: inductor selection. the inductor should be chosen such that it can handle the necessary input current. in most applica- tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range.
wide input voltage range, high efficiency fault tolerant led driver a8513 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 4a: determine the duty cycle: d (max) v d = + v in (min) v out(ovp) 78% == 22.32 v + 0.4 v 1 ? 1 ? 5 v (14) where v d is the voltage drop of the boost diode. step 4b: determine the maximum and minimum input current to the system. the minimum input current will dictate the inductor value. the maximum current rating will dictate the current rating of the inductor. given i out = i led = 120 ma: i in (max) = v in (min) v out(ovp) i out h 0.595 a == 22.32 v 5 v 0.9 120 ma (15) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 0.19 a == 22.32 v 16 v 0.9 120 ma (16) a good approximation of efficiency can be taken from the effi- ciency curves located in the data sheet. a value of 90% is a good starting approximation. step 4c: determine the inductor value. to assure that the inductor operates in continuous conduction mode the value of inductor should be set such that the ? inductor ripple current is not greater than the average minimum input cur- rent. a good inductor choice for inductor ripple current is 30% of the maximum input current: i l = i in (max) 0.3 (17) = 0.595 a 0.3 = 0.18 a then: l = v in (min) d (max) f sw i l 10.83 h 0.18 a == 0.78 5 v 2 mhz (18) double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (19) 0.19 a > 0.09 a a good inductor value to use would be 10 h. step 4d: this step verifies that there is sufficient slope compensa- tion for the inductor chosen. the required slope compensation value for different frequencies is listed below: f sw (mhz) slope compensation (a/ s) 2 3.73 1 1.85 0.500 3.70 0.250 1.83 next insert the inductor value used in the design: = v in (min) d (max) f sw l used i lused 10 h 0.20 a == 0.78 5 v 2.0 mhz (20) calculate the minimum required slope: = (1 ? d (max)) (1 ? 0.78) f sw required slope (min) i lused 0.20 a 1 1 1 10 ? 6 110 ? 6 == 1.8 a/ s 2.0 mhz (21)
wide input voltage range, high efficiency fault tolerant led driver a8513 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for a stable system, the required minimum slope must be smaller than the ic slope compensation. note: the slope compensation value is in a/ s; the 1 10 -6 is a constant multiplier. step 4e: determine the inductor current rating : i l minimum rating = i in (max) + 1 / 2 i lused (22) = 0.595 a + 0.20 a / 2 = 0.695 a step 5: choose the proper switching diode. the switching diode should be chosen for three characteristics when it is used in led lighting circuitry. the first and most obvious are the current rating of the diode and the reverse voltage rating. the reverse voltage rating should be such that during operation condition the voltage rating of the device is larger than the maximum output voltage; in this case it is v out (ovp) . the peak current through the diode is: i dp = i in (max) + 1 / 2 i lused (23) = 0.595 a + 0.20 a / 2 = 0.695 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. step 6: choose the output capacitors. the output capacitors should be chosen such that they provide filtering for both the boost converter and for the pwm dimming function. the biggest factors that contribute to the size of the output capacitor is pwm dimming frequency and the pwm duty cycle. another major contributor is leakage current, i lkg . this current is a combination of the ovp resistor divider, i ovp , and the reverse leakage of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically the voltage variation on the output during pwm dimming must be less than 250 mv (v cout ) so that no audible noise can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d dimming (min) 1 ? 0.01 200 hz i lkg 120 a 2.38 f == 0.250 v v cout (24) a capacitor larger than 2.38 f capacitor should be selected due to degradation of capacitance at high voltages on the capacitor. one ceramic 4.7 f, 50 v capacitor is a good choice to fulfill this requirement. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) + ? i l i out 0.120 a 0.23 a 12 == i in (max) 1 ? 0.78 0.78 + 0.20 a 0.595 a 12 (25) the output capacitor should have a current rating of at least 230 ma. the current rating of the 4.7 f, 50v capacitor is 1.5 a.
wide input voltage range, high efficiency fault tolerant led driver a8513 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw ovp vout r ovp1 r ovp2 vin vdd c vdd c out en/pwm iset gnd comp led fault pad a8513 r z c z v c r iset c in 4.7 f 50 v 4.7 f 50 v 0.47 f 10 h 0.1 f 120 pf 100 k 8.66 k 120 422 k 24.3 k l1 d1 c p v in step 7: select the input capacitor. the input capacitor should be selected such that it provides good filtering of the input voltage waveform. a good rule of thumb is to set the input voltage ripple, v in to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.20 a ? i l 0.25 f 8 == ? v in 2 mhz 0.05 v 8 (26) the rms current through the capacitor is given by: i in rms = (1 ? d (max)) i out ? i l 0.05 a 12 = = i in (max) (1 ? 0.78) 0.120 0.20 a 0.595 a 12 (27) a good ceramic input capacitor with ratings of 2.2 f, 50v or 4.7 f, 50 v will suffice for this application. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l figure 21. a typical circuit designed using the example above in this section.
wide input voltage range, high efficiency fault tolerant led driver a8513 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical application drawings sw ovp vout r ovp1 r ovp2 vin vdd c vdd c out en/pwm iset gnd comp led fault pad a8513 r z (optional) c z (optional) r iset c in r p r7 l1 r1 d1 c p v in r1 is used to provide a leakage path such that the ovp pin is above 100 mv during startup. otherwise the ic would assume the output is shorted to gnd and would not proceed with soft start. a a sw ovp vout r ovp1 r ovp2 vin vdd c vdd c out c sw en/pwm iset gnd comp led fault pad a8513 r z (optional) c z (optional) v c r iset c in l1 r1 l2 d1 d2 c p v in = 9 to 16 v r1 is used to provide a leakage path such that the ovp pin is above 100 mv during startup. otherwise the ic would assume the output is shorted to gnd and would not proceed with soft start. d2 is a blocking diode. a b a b figure 22. typical application showing boost configuration and pmos disconnect switch implementation figure 23. typical application showing sepic configuration
wide input voltage range, high efficiency fault tolerant led driver a8513 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 16-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 16x 0.65 bsc 0.25 bsc 2 1 16 5.000.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 abt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b c exposed thermal pad (bottom surface); dimensions may vary with device 6.10 0.65 0.45 1.70 3.00 3.00 16 2 1 reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c branded face 3 nom 3 nom
wide input voltage range, high efficiency fault tolerant led driver a8513 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ly, 10-pin msop with exposed thermal pad terminal #1 mark area a gauge plane seating plane 0.86 0.05 seating plane 0.50 ref 0.25 2 1 10 2 1 10 a b c c 0.53 0.10 0.15 0.05 0.05 0.15 0 to 6 3.00 0.10 3.00 0.10 4.88 0.20 1.73 4.60 1.98 1.98 min 1.73 2 1 10 1 0.30 0.50 1.65 0.27 0.18 for reference only; not for tooling use (reference jedec mo-187ba-t) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b exposed thermal pad (bottom surface) reference land pattern layout (reference ipc7351 sop50p490x110-11m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5)
wide input voltage range, high efficiency fault tolerant led driver a8513 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2011-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. revision history revision revision date description of revision rev. 2 january 18, 2012 update features list

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